/**
 * Decoder will generate all the control signal for further pipeline stage.
 **/

module Decoder(opcode,
               // signal for excute
               aluop,
               aluimm,
               alusrc2_sel,
               // signal for mem
               mem_wen,
               // signal for writeback
               reg_wen,
               reg_waddr,
               wb_sel,
               isjeq,
               isjlt
               );
   input wire [31:0] opcode;
   output wire [3:0] aluop;
   output wire [15:0] aluimm;
   output wire        alusrc2_sel;
   output wire        reg_wen;
   output wire [4:0]  reg_waddr;
   output wire        mem_wen;
   output wire        isjeq;
   output wire        isjlt;

   //
   output wire        wb_sel;

   assign aluop = opcode[27:24];
   assign aluimm = opcode[15:0];
   assign alusrc2_sel = opcode[31];
   assign reg_wen = (opcode[31:28] == 4'b0010) || (opcode[31:28] == 4'b1001) || (opcode[31:28] == 4'b0000);
   assign reg_waddr = (opcode[31:28] == 4'b0010)*opcode[13:9] + (opcode[31:28] == 4'b1001)*opcode[23:19] + (opcode[31:28] == 4'b0000)*opcode[13:9];
   assign mem_wen = opcode[31:28] == 4'b0011 && opcode[27:24] == 4'b0000;
   assign isjeq = (opcode[31:28] == 4'b0101);
   assign isjlt = (opcode[31:28] == 4'b0111);

   // load 00100000
   assign wb_sel = (opcode[31:28]==4'b0010) && (opcode[27:24]==4'b0000);

endmodule
